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1 ISL97676 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. 6-channel led driver with phase shift control ISL97676 the ISL97676 is an led driver that drives 6 channels of led current for tft-displa y. the ISL97676 drives 6 channels of led to support 78 leds from 4.5v to 26v or 48 leds from a boost supply of 2.7v to 26v and a separate 5v bias supply on the ISL97676 vin pin. the ISL97676 compensates fo r non-uniformity of the forward voltage drops in the led strings with its 6 voltage controlled-current source channels. its headroom control monitors the highest led forward voltage string for output regulation, to minimize the voltage headroom and power loss in the typical multi string operation. intersil offers two pwm di mming modes: the ISL97676 digitizes the incoming pwm signal and provides 8-bit dimming. the pwm frequenc y is set by a resistor providing dimming frequency between 100hz to 30khz. secondly, direct pwm mode wi thout phase shift, where the dimming follows the input pwm signal. the ISL97676 features channe l phase shift control to minimize the input, output ripple characteristics and load transients as well as spreading the light output to help eliminate or reduce the video and audio noise interference from the backlight driver operation. features ? 6 channels ? channel phase shift pwm dimming ? direct pwm dimming without phase shift ? 4.5v to 26v input ?45v output max ? up to 30ma led current per channel ? drive up to 78 (3.2v/20ma each) leds ? current matching of 1.5 % from 1% ~ 100% dimming ? dynamic headroom control ?protections - string open/short circuit, v out short circuit overvoltage, and over-temperature protections - optional master fault protection ? selectable 600khz or 1.2mhz switching frequency ? 20 ld qfn 4mmx4mm package applications ? netbook displays led backlighting ? notebook displays led backlighting typical application circuit en v in * = 4.5~26v comp nc vin ovp fsw/ v out = 45v*, 30ma per string vddio fb1 fb4 fb3 fb5 fb6 iset 19 1 2 18 3 4 6 7 8 10 11 12 14 5 sw 16 pgnd 15 agnd 9 ISL97676 fb2 rfpwm// 13 *for v in > 6v fault 17 20 pwm directpwm phaseshift march 12, 2010 fn7600.0
ISL97676 2 fn7600.0 march 12, 2010 block diagram ref gen gm amp comp + - + - fb1 fb6 logic fet driver ovp sw ISL97676 osc & ramp comp s = 0 imax ilimit vddio temp sensor pwm pgnd iset + - gnd vin reg o/p short ref ovp ref vsc 4.75v bias + - 10h/3a 4.7f/50v fb2 open ckt, short ckt detects 8-bit digitizer 1 2 fpo ovp 6 vset phase select phase shift & pwm controller fsw/ phaseshift highest vf string detect dynamic headroom control 8-bit dac en fpwm/directpwm fault optional pfet fault fet drv * v in > = 6v directpwm detect fsw detect phase select vin* = 4.5v~26v 45v*/30ma per string 78 (6x13) leds shutdown
ISL97676 3 fn7600.0 march 12, 2010 pin configuration ISL97676 (20 ld qfn) top view pwm vin comp fault fb5 fb4 agnd fb3 vddio en fsw/phaseshift iset nc pgnd ovp rfpwm/directpwm fb1 fb2 1 2 3 4 5 15 14 13 12 11 20 19 18 17 78910 ISL97676 4mmx4mm sw 16 6 fb6 pin descriptions (i = input, o = output, s = supply) pin name pin no. type description vddio 1 s decouple with capacitor for internally generated supply rail. en 2 i enable fsw/phaseshift 3 i fsw = 0 ~ 0.25 * vddio, boost sw itching frequency = 600khz with phase shift. fsw = 0.25 * vddio ~ 0.5 * vddio, boost switching frequency = 600khz without phase shift. fsw = 0.5 * vddio ~ 0.75 * vddio, boost switching frequency = 1.2mhz without phase shift. fsw = 0.75 * vddio ~ vddio, boost swit ching frequency = 1.2mhz with phase shift. iset 4 i resistor connection for setting led curr ent, (see equation 3 for calculating the i led peak). nc 5 i no connect. fb6 6 i input 6 to current so urce, fb, and monitoring. fb5 7 i input 5 to current so urce, fb, and monitoring. fb4 8 i input 4 to current so urce, fb, and monitoring. agnd 9 s analog ground for precision circuits. fb3 10 i input 3 to current source, fb, and monitoring. fb2 11 i input 2 to current source, fb, and monitoring. fb1 12 i input 1 to current source, fb, and monitoring. rfpwm/directpwm 13 i external pwm dimming with frequ ency modulation or direct pwm dimming without frequency modulation. when this pin is not biased and a resistor is connected to ground, the dimming frequency will be set by the setting resistor. when this pin is floating, the part enters direct pwm mode such that the dimming follows the input pwm signal without frequency modulation. ovp 14 i overvoltage protection input. pgnd 15 s power ground (lx power return).
ISL97676 4 fn7600.0 march 12, 2010 sw 16 o input to boost switch. fault 17 o gate drive signal for external fault mo sfet. this pin should be left floating when fault mosfet is omitted in the application. comp 18 i external compensation pin. vin 19 s led driver supply voltage. pwm 20 i pwm brightness control pin. epad 21 i connect epad to junction of agnd an d pgnd with adequate vias to form a star ground. pin descriptions (i = input, o = output, s = supply) (continued) pin name pin no. type description ordering information part number (notes 1, 2) part marking temp range (c) package (pb-free) pkg. dwg. # ISL97676irz 976 76irz -40 to +85 20 ld 4x4 qfn l20.4x4c notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for ISL97676 . for more information on msl please see techbrief tb363 .
ISL97676 5 fn7600.0 march 12, 2010 table of contents typical application circuit .................................................................................................... ............... 1 block diagram .................................................................................................................. ................... 2 pin descriptions (i = input, o = output, s = supply) .......................................................................... 3 absolute maximum ratings ....................................................................................................... .......... 6 thermal information ............................................................................................................ ............... 6 operating conditions ........................................................................................................... ................ 6 electrical specifications ...................................................................................................... ................. 6 typical performance curves ..................................................................................................... ........... 9 theory of operation............................................................................................................ ............... 12 pwm boost converter ............................................................................................................ .......... 12 ovp ............................................................................................................................ .................. 12 enable ......................................................................................................................... .................. 12 power sequence ................................................................................................................. ............ 12 current matching and current accuracy .......................................................................................... ... 12 dynamic headroom control ....................................................................................................... ....... 12 dimming controls ............................................................................................................... ............ 12 maximum dc current setting ..................................................................................................... ...... 12 pwm control.................................................................................................................... ............... 13 phase shift control............................................................................................................ .............. 13 pwm dimming frequency adjustment ............................................................................................... . 14 direct pwm dimming ............................................................................................................. .......... 14 switching frequency............................................................................................................ ............ 14 inrush control and soft-start .................................................................................................. ......... 14 fault protection and monitoring ................................ ................................................................ ......... 15 short circuit protection (scp) ................................................................................................. .......... 15 open circuit protection (ocp) .................................................................................................. ......... 15 overvoltage protection (ovp) ................................................................................................... ........ 15 undervoltage lockout ........................................................................................................... ........... 15 master fault protection ........................................................................................................ ............ 15 over-temperature protection (otp).............................................................................................. ..... 16 components selections .......................................................................................................... .......... 17 input capacitor................................................................................................................ ............... 18 inductor ....................................................................................................................... ................. 18 output capacitors .............................................................................................................. ............. 18 channel capacitor .............................................................................................................. ............. 18 output ripple .................................................................................................................. ............... 18 schottky diode ................................................................................................................. .............. 19 applications................................................................................................................... .................... 19 high current applications ...................................................................................................... ........... 19 revision history ............................................................................................................... ................. 19 products ....................................................................................................................... ..................... 19 package outline drawing ........................................................................................................ .......... 20
ISL97676 6 fn7600.0 march 12, 2010 absolute maximum ratings (t a = +25c) thermal information vin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 28v fault, en . . . . . . . . . . . . . . . -0.3v to min(28, vin + 0.3)v fsw/phaseshift, rfpwm/directpwm, ovp . . . . -0.3v to 5.5v vddio, pwm, comp . . . . . . . -0.3v to min(5.5, vin + 0.3)v iset . . . . . . . . . . . . . . . . -0.3v to min(vddio + 0.3, 5.5)v fb1, fb2, fb3, fb4, fb5, fb6 . . . . . . . . . . . . . -0.3v to 45v sw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 46v pgnd, agnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v above voltage ratings are all with respect to agnd pin esd rating human body model (tested per jesd22-a114e) . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . 1kv thermal resistance (typical) ja (c/w) jc (c/w) 20 ld qfn package (notes 4, 5, 7) . 39 2.5 thermal characterization (typical) psi jt (c/w) 20 ld qfn package (note 6) . . . . . . . . . . . . 3 maximum continuous junction temperature . . . . . . +125c storage temperature . . . . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. psi jt is the psi junction-to-top thermal characterization parameter. if the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the jc and jc thermal resistance ratings. 7. refer to jesd51-7 high effective thermal conductivity board layout for proper via and plane designs. electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en = 3.3v, r iset = 19.6k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter condition min (note 8) typ max (note 8) unit general v in (note 9) backlight supply voltage 4.5 26 v ivin_stby v in shutdown current en = 0v 10 a v out output voltage 4.5v < v in 26v, f sw = 600khz 45 v 6.75v < v in 26v, f sw = 1.2mhz 45 v 4.5v < v in 6.75v, f sw = 1.2mhz v in /0.15 v v uvlo undervoltage lockout threshold 2.6 3.1 3.3 v v uvlo_hys undervoltage lockout hysteresis 320 mv regulator v ddio ldo output voltage v in > 5.5v 4.6 4.8 5 v i vddio_stby standby current en = 0v 10 a i vin driver input current 100% dimming 9 ma v ldo vddio ldo dropout voltage v in >5.5v, i vddio = 20ma 30 200 mv en low guaranteed range for en input low voltage 0.5 v en hi guaranteed range for en input high voltage 1.8 v t enlow en low time before shut-down 29.5 ms
ISL97676 7 fn7600.0 march 12, 2010 boost swilimit boost fet current limit 1.5 2.2 2.7 a r ds(on) internal boost swit ch on-resistance t a = +25c 230 300 m ss soft-start 100% led duty cycle 14 ms eff_peak peak efficiency v in = 12v, 72 leds, 20ma each, l = 10h with dcr 101m , t a = +25c 92 % i out / v in line regulation 0.1 % d max boost maximum duty cycle fsw < 0.5 * vddio 91 % fsw > 0.5 * vddio 82 % d min boost minimum duty cycle fsw < 0.5 * vddio 8.5 % fsw > 0.5 * vddio 16.5 % f sw boost switching frequency fsw <0.5 * vddio 475 600 640 khz fsw >0.5 * vddio 950 1200 1280 khz isw_leakage sw leakage current sw = 45v, en = 0 10 a current sources i match dc channel-to-channel current matching r iset = 19.6k , (i out = 20ma) -1.5 +1.5 % r iset = 39.2k , (i out = 10ma) -1.5 +1.5 % i acc current accuracy r iset = 19.6k , (i out = 20ma) -1.5 +1.5 % v headroom dominant channel current source headroom at fbx pin 500 mv v iset voltage at i set pin 1.2 1.22 1.24 v i ledmax maximum led current pe r channel 6-channel, v in =4.5v, v out = 40v, f sw = 600khz 30 ma pwm interface v il guaranteed range for pwm input low voltage 0.8 v v ih guaranteed range for pwm input high voltage 1.5 v fpwmi pwmi input frequency range 100 30,000 hz pwmacc pwmi input accuracy 8 bits pwmhyst pwmi input allowable jitter hysteresis -0.46 +0.46 lsb pwm generator fpwm pwm dimming frequency range rfpwm = 1.5m 45 50 55 hz rfpwm = 1.5k 33 37 39 khz vrfpwm voltage at rfpwm pin 1.19 1.22 1.24 v t min minimum on time direct pwm mode 250 350 ns electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en = 3.3v, r iset = 19.6k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter condition min (note 8) typ max (note 8) unit
ISL97676 8 fn7600.0 march 12, 2010 fault detection v sc channel short circuit threshold 3.15 3.6 4.3 v v temp_acc over-temperature threshold accuracy 5 c v temp_shdn over-temperature shutdown 150 c v ovplo overvoltage limit on ovp pin 1.2 1.22 1.24 v ovp fault ovp short detection fault level 350 mv i fault fault pull-down current v in = 12v 8 15 25 a v fault fault clamp voltage with respect to v in v in = 12, v in - v fault 6 7 8.3 v swstart_thres sw start-up threshold 1.2 1.4 1.5 v isw_startup sw start-up current 1 3.5 5 ma notes: 8. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characterization and ar e not production tested. 9. at minimum v in of 4.5v, the maximum output is limited by the v out specifications. also at maximum v in of 26v, the minimum v out is 28v but minimum v out can be lower at lower v in . in general, the v in and v out relationship is bounded by d max and d min . electrical specifications all specifications below are tested at t a = +25c; v in = 12v, en = 3.3v, r iset = 19.6k , unless otherwise noted. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter condition min (note 8) typ max (note 8) unit
ISL97676 9 fn7600.0 march 12, 2010 typical performance curves figure 1. efficiency vs 20ma led current (100% led duty cycle) vs v in figure 2. efficiency vs 30ma led current (100% led duty cycle) vs v in figure 3. efficiency vs v in vs switching frequency at 20ma (100% led duty cycle) figure 4. efficiency vs v in vs switching frequency at 30ma (100% led duty cycle) figure 5. efficiency vs v in vs temperature at 20ma (100% led duty cycle) figure 6. efficiency vs v in vs temperature at 30ma (100% led duty cycle) 0 20 40 60 80 100 0 5 10 15 20 25 i led (ma) efficiency (%) 24v in 12v in 5v in 0 20 40 60 80 100 0 5 10 15 20 25 30 35 i led (ma) efficiency (%) 24v in 12v in 5v in 0 5 10 15 20 25 30 v in (v) 20ma/1.2mhz 20ma/582khz 0 20 40 60 80 100 efficiency (%) 0 20 40 60 80 100 efficiency (%) 30ma/1.2mhz 30ma/582khz 0 5 10 15 20 25 30 v in (v) 70 75 80 85 90 95 0 5 10 15 20 25 30 output load (ma) efficiency (%) +85c -40c 0c +25c 80 82 84 86 88 90 92 94 0 5 10 15 20 25 30 efficiency (%) v in (v) +85c -40c 0c +25c
ISL97676 10 fn7600.0 march 12, 2010 figure 7. channel-to-channel current matching figure 8. current linearity vs low level pwm dimming duty cycle vs v in figure 9. quiescent current vs v in vs temperature with/shut enable figure 10. v headroom vs v in vs temperature at 20ma figure 11. v out ripple voltage, v in = 12v, 6p12s at 20ma/channel figure 12. in-rush and led current at v in = 6v for 6p12s at 20ma/channel typical performance curves (continued) -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 channel current matching(%) 21v in 123456 07 12v in 4.5v in 0 0.2 0.4 0.6 0.8 1.0 1 dc (%) i led ma 4.5v in 23456 0 12v in 5 6 7 8 9 10 0 5 10 15 20 25 30 i in (ma) v in (v) 0.40 0.45 0.50 0.55 0.60 0 5 10 15 20 25 30 v headroom (v) -40c 0c +25c v in (v)
ISL97676 11 fn7600.0 march 12, 2010 figure 13. in-rush and led current at v in = 12v for 6p12s at 20ma/channel figure 14. line regulation with v in change from 6v to 26v, v in = 12v, 6p12s at 20ma/channel figure 15. line regulation with v in change from 26v to 6v for 6p12s at 20ma/channel figure 16. load regulation with i led change from 0% to 100% pwm dimming, v in = 12v, 6p12s at 20ma/channel figure 17. load regulation with i led change from 100% to 0% pwm dimming, v in = 12v, 6p12s at 20ma/channel figure 18. ISL97676 shuts down and stops switching ~ 30ms after en goes low typical performance curves (continued)
ISL97676 12 fn7600.0 march 12, 2010 theory of operation pwm boost converter the current mode pwm boost converter produces the minimal voltage needed to enable the led stack with the highest forward voltage drop to run at the programmed current. the ISL97676 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. such architecture achieves a fast transient response that is essential for the notebook backlight application. the input power may instantly change when the user switches from a drained battery to a ac/dc adapter without causing any flicker in the display backlight. the ISL97676 is capable of boosting up to 45v and typically can drive 13 (3.2v/20ma) leds in series on each of the 6 channels from a 4.5v input. ovp the overvoltage protection (ovp) pin has a function of setting the overvoltage trip level as well as limiting the v out regulation range. the ISL97676 ovp threshold is set by r upper and r lower such that: and v out can only regulate between 64% and 100% of the v out _ovp such that: for example, if 10 leds are used with the worst case v out of 35v, and r upper and r lower are chosen such that the ovp level is set at 40v, then the allowed v out range is between 25.6v and 40v. if the requirement is changed to 6 leds/channel for a maximum v out of 21v, then the ovp level must be reduced according to equation 2 to accomodate the new reduced output voltage. otherwise, the headroom control will be disturbed and the channel voltage may be higher and prevent the driver from operating properly. the ratio of the ovp capacitors should be the inverse of the ovp resistors. for example, if r upper / r lower = 33/1, then c upper / c lower = 1/33. for example , if c upper = 100pf then c lower = 3.3nf. enable an en signal is required to enable the internal regulator for normal operation. if there is no signal longer than 28ms, the device will enter shutdown. power sequence there is no specific power sequence requirement for the ISL97676. the en signal can be tied to v in but not the vddio as it will prevent the device from powering up. current matching an d current accuracy each channel of the led current is regulated by the current source circuit, as shown in figure 19. the led peak current is set by translating the r iset current to the output with a scaling factor of 392/r iset . the drain terminals of the current source mosfets are designed to run at ~ 500mv to minimize power loss. the sources of errors for the channel-to-channel current matching are due to internal mismatches, offsets and the external r iset resistor. to minimize this external offset, a 1% tolerance resistor is recommended. dynamic headroom control the ISL97676 features a prop rietary dynamic headroom control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the fb1-6 pins digitally. this lowest fb voltage is used as the feedback signal for the boost regulator. since all led stacks are connected in parallel to the same output voltage, the other fb pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same current. the output voltage will regulate cycle by cycle and it is always referenced to the highest forward voltage string in the architecture. dimming controls the ISL97676 allows two ways of controlling the led current, and therefore, the brightness. they are: 1. dc current adjustment. 2. pwm chopping of the led current defined in step 1. maximum dc current setting the initial brightness should be set by choosing an appropriate value for r iset . this should be chosen to fix the maximum possible led current: for example, if the maxi mum required led current (i led(max) ) is 20ma, rearranging equation 3 yields equation 4: (eq. 1) v out _ovp 1.21v r upper r lower + () r lower ? = (eq. 2) a llowable v out 64% to 100% of v out _ovp = figure 19. simplified current source circuit ref + - pwm dimming + ref + - r iset - i ledmax 392 () r iset ---------------- - = (eq. 3) r iset 392 () 0.02 ? 19.6k == (eq. 4)
ISL97676 13 fn7600.0 march 12, 2010 pwm control the ISL97676 has a high speed 8-bit digitizer that decodes an incoming pwm signal and converts it into six channels of 8-bit pwm cu rrent with a phase shift function that will be descri bed later. during the pwm on period, the led peak current is defined by the value of r iset resistor, the average led current of each channel is controlled by i ledmax and the pwm duty cycle in percent as: when the pwm input = 0, all channels are disconnected and the i led is guaranteed to be <10a in this state. the pwm dimming frequency is adjusted by a resistor at the rfpwm pin, which will be described in ?pwm dimming frequency adjustment? on page 14. phase shift control the ISL97676 is capable of delaying the phase of each current source. conventional led drivers pose the worst load transients to the boost circuit by turning on all channels simultaneously as shown in figure 20. in contrast, the ISL97676 phase shifts each channel by turning them on once during each pwm dimming period as shown in figure 21. at each dimming duty cycle except at 100%, the sum of the phase shifted channel currents will be less than a conventional led driver as shown in figure 22 and 23. equal phase means there is fixed delay between channels and such delay can be calculated as: i led ave () i ledmax pwm = (eq. 5) figure 20. conventional led driver with 10% pwm dimming channel current (upper) and total current (lower) time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma 200ma sel>> figure 21. phase shift led driver with 10% pwm dimming channel current (upper) and total current (lower) time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5)+120m i(i6)+150m 0a 100ma 200ma figure 22. conventional led driver vs phase shift led driver pwm dimming channel and total current at 10% to 30% time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma sel>> i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1) i( i 2 ) +3 0 m i(i3)+60m i(i4)+90m i( i 5 ) + 12 0 m i(i6)+150m 0a 100ma 200ma ti m e 0s 2ms 4ms 6ms 8ms 10 m s 12 m s 14 m s 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma sel>> ti m e 0s 2ms 4ms 6ms 8ms 10 m s 12 m s 14 m s 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i( i 5 )+ 1 2 0m i(i6)+150m 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5)+120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1) i( i 2 ) +3 0 m i(i3)+60m i(i4)+90m i( i 5 ) + 12 0 m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5)+120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14 m s 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5)+120m i(i6)+150m 0a 100ma 200ma sel>> 10% 20% 30% figure 23. conventional led driver vs phase shift led driver pwm dimming total current at 40% to 100% ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2m s 4m s 6m s 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i 6) 0a 100ma 200ma time 0s 2m s 4m s 6m s 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i (i4)+90m i(i5)+120m i(i6)+150m 0a 100ma 200ma sel>> ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma 200ma sel>> ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma 200ma sel>> ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma 200ma sel>> ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma sel>> ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i 5)+120m i(i6)+150m 0a 100ma ti me 0s 2ms 4ms 6ms 8ms 10 ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma 200ma sel>> time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1) i(i2)+30m i(i3)+60m i(i4)+90m i(i5) +120m i(i6)+150m 0a 100ma time 0s 2ms 4ms 6ms 8ms 10ms 12ms 14ms 16ms 18ms 20ms i(i1)+i(i2)+i(i3)+i(i4)+i(i5)+i(i6) 0a 100ma sel>> 40% 50% 60% 70% 80% 90% 100% t d1 t fpwm 255 () ------------------ - x 255 n --------- - ?? ?? = (eq. 6) t d2 t fpwm 255 ------------------ - x 255 () n1 ? () 255 n --------- - ?? ?? ? ?? ?? = (eq. 7)
ISL97676 14 fn7600.0 march 12, 2010 where ( 255/n ) in equation 6 and equation 7 can only be integer because the pwm dimming is controlled by an internal 8-bit digital counter. as a result, any decimal value of (255/n) will be discarded. for example for n = 6, ( 255/n ) = 42, thus: where t fpwm is the sum of t on and t off . n is the number of active channels. the ISL97676 will detect the numbers of active channels automatically and is illustrated in figure 25 for 6-channels and figure 26 for 4-channels. . pwm dimming frequency adjustment the dimming frequency is set by an external resistor at the rfpwm/directpwm pin to gnd: where fpwm is the desirable pwm dimming frequency and r fpwm is the setting resistor. do not bias rfpwm/directpwm if direct pwm dimming is used, see table 1 for clarifications. the pwm dimming frequency can be set or applied up to 30khz with duty cycle from 0.4% to 100%. direct pwm dimming the ISL97676 can also operate in direct pwm dimming mode such that the output follows the input pwm signal without phase shifting and dimming frequency modifications. to use direct pwm mode, users should float rfpwm/directpwm pin. the input pwm frequency should be limited to 30khz. switching frequency when the fsw/phaseshift pin is biased from vddio with a resistor divider r upper and r lower , the switching frequency and phase shift func tion will change according to the following fsw/phaseshift levels shown in table 2 with the recommended r upper and r lower values . inrush control and soft-start the ISL97676 has separate built-in independent inrush control and soft-start functions. the inrush control function is built around the short circuit protection fet, and is only available in applications which include this device. after an initial delay from the point where the master fault protection fet is turned on, it is assumed that inrush has completed. at this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. the current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. the ISL97676 includes a soft-start feature where this current limit starts at a low value (275ma). this is stepped up to the final 2.2a current limit in 7 further steps of 275ma. these steps will happen over at least 8ms, and will be extended at low led pwm frequencies if the led duty cycle is low. this allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. t d1 t fpwm 42 255 --------- - = (eq. 8) t d2 t fpwm 45 255 --------- - = figure 24. 6 equal phase channels phase shift illustration iled1 iled2 iled3 iled4 iled5 iled6 iled1 t on t off pwmi 60% 40% 60% 40% t d1 t d1 t d1 t d1 t d1 t d2 t fp w m (t pwmout ) t d1 = fixed delay with integer only while the decimal value will be discarded (eg. 42.5=42) figure 25. 4 equal phas e channels phase shift illustration iled1 iled2 iled3 iled4 iled1 t on t off pwmi 60% 40% 60% 4 0% t d1 t d1 t d1 t d2 t pwmin t fp w m (t pwm out ) t d1 = fixed delay with integer only while the decimal value will be discarded (eg. 63.75=63) f pwm 6.66 7 10 rfpwm ------------------------ = (eq. 9) table 1. rfwm/directpwm function phaseshift connects with resistor pwm dimming with frequency adjust yes floating directpwm without frequency adjust no table 2. fsw/phase shift level switching frequency phase shift r upper r lower 0 ~ 0.25 * vddio 600khz yes open 0 0.25 * vddio ~ 0.5 * vddio 600khz no 150k 100k 0.5 * vddio ~ 0.75 * vddio 1.2mhz no 100k 150k 0.75 * vddio ~ vddio 1.2mhz yes 0 open
ISL97676 15 fn7600.0 march 12, 2010 for systems with no master fault protection fet, the inrush current will flow towards c out when v in is applied and it is determined by the ramp rate of v in and the values of c out and boost inductor, l. fault protection and monitoring the ISL97676 features extensive protection functions to cover all the perceivable failure conditions. the failure mode of an led can be either open circuit or as a short. the behavior of an open circuited led can additionally take the form of either infinite resistance or, for some leds, a zener diode, which is integrated into the device in parallel with the now opened led. for basic leds (which do not have built-in zener diodes), an open circuit failure of an led will only result in the loss of one channel of leds without affecting other channels. similarly, a led short circuit condition which causes the fb voltage to rise to ~4v, will result in that channel turning off. this does not affect any other channels. due to the lag in boost response to any load change at its output, certain transient events (such as led current steps or significant step changes in led duty cycle) can transiently look like led fault modes. the ISL97676 uses feedback from the leds to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the led stacks to fault out. see table 3 for more details. a fault condition that results in high input current due to a short on v out with master fault protection switch will result in a shutdown of all output channels. the control device logic will remain functional. short circuit protection (scp) the short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. when an led becomes shorted, the action taken is described in table 3. the short circuit threshold is 4v. open circuit protection (ocp) when one of the leds becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. the ISL97676 monitors the current in each channel such that any string which reaches the intended output current is considered ?good?. should the current subsequently fall below the target, the channel will be considered an ?open circuit?. furthermore, should the boost output of the ISL97676 reach the ovp limit or should the lower over-temperature threshold be reached, all channels which are not ?good? will immediately be considered as ?open circuit?. detection of an ?open circuit? channel will result in a time-out before disabling of the affected channel. this time-out is run when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. some users employ special types of leds that have zener diode structure in para llel with the led for esd enhancement, thus enabling open circuit operation. when this type of led goes open circuit, the effect is as if the led forward voltage has increased, but no light is emitted. any affected string will not be disabled, unless the failure results in the boost ovp limit being reached, allowing all other leds in the string to remain functional. care should be taken in this case that the boost ovp limit and scp limit are set properly, to make sure that multiple failures on one string do not cause all other good channels to be faulted out. this is due to the increased forward voltage of the faulty channel making all other channels look as if they have led shorts. see table 3 for details for responses to fault conditions. overvoltage protection (ovp) the integrated ovp circuit mo nitors the output voltage and keeps the voltage at a safe level. the ovp threshold is set as: these resistors should be large to minimize the power loss. for example, a 1m r upper and 30k r lower sets ovp to 41.2v. large ovp resistors also allow c out discharges slowly during the pwm off time. parallel capacitors should also be placed across the ovp resistors such that r upper /r lower = c lower /c upper . using a c upper value of at least 30pf is recommended. these capacitors reduce the ac impedance of the ovp node, which is important when using high value resistors. undervoltage lockout if the input voltage falls below the uvlo level of 3.1v, the device will stop switching and be reset. operation will restart once the input voltage is back in the normal operating range. master fault protection during normal switching operation, the current through the internal boost power fet is monitored. if the input current exceeds the current limit due to output shorted to ground or excessive loading, the internal switch will be turned off. this monitoring happens on a cycle by cycle basis in a self protecting way. additionally, the ISL97676 monitors the voltage at the lx and ovp pins. at start-up, a fixed current is injected out of the lx pins and into the output capacitor. the device will not start up unless the voltage at lx exceeds 1.2v. the ovp pin is also monitored such that if it rises above and subsequently falls below 20% of the target ovp level, the input protection fet will be switched off. ovp 1.21v r upper r lower + () r lower ? = (eq. 10)
ISL97676 16 fn7600.0 march 12, 2010 over-temperature protection (otp) the ISL97676 includes two ov er-temperature thresholds. the lower threshold is set to +130c. when this threshold is reached, any channel which is outputting current at a level below the regulation target will be treated as ?open circuit? and disabled after a time-out period. the intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. the upper threshold is set to +150c. each time this is reached, the boost will stop switching and the output current sources will be switched off. for the extensive fault protection conditions, please refer to figure 26 and table 3 for details. table 3. protections table case failure mode detection mode failed channel action good channels action v out regulated by 1 fb1 short circuit upper over-temperature protection limit (otp) not triggered and fb1 < 4v fb1 on and burns power. fb2 through fb6 normal highest vf of fb2 through fb6 2 fb1 short circuit upper otp triggered but vfb1 < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce i out further. same as fb1 highest vf of fb2 through fb6 3 fb1 short circuit upper otp not triggered but fb1 > 4v fb1 disbled after 6 pwm cycle timeout. fb2 through fb6 normal highest vf of fb2 through fb6 figure 26. simplified fault protections q6 vsc fb6 v set pwm1/oc1/sc1 ref fet driver i max i limit driver fault ovp v in t2 otp thrm shdn q1 vsc fb1 v out phase shift & control logic v set pwm6/oc6/sc6 temp sensor logic lx t1 otp thrm shdn o/p short + - + - reg v set /2 v in
ISL97676 17 fn7600.0 march 12, 2010 components selections according to the inductor voltage-second balance principle, the change of inductor current during the switching regulator on-time is equal to the change of inductor current during the switching regulator off-time. since the voltage across an inductor is: and i l @ t on = i l @ t off , therefore: where d is the switching duty cycle defined by the turn-on time over the switching period. v d is schottky diode forward voltage which can be neglected for approximation. rearranging the terms without accounting for v d gives the boost ratio and duty cycle respectively as: 4 fb1 open circuit with infinite resistance upper otp not triggered and fb1 < 4v v out will ramp to ovp. fb1 will time-out after 6 pwm cycles and switch off. v out will drop to normal level. fb2 through fb6 normal highest vf of fb2 through fb6 5fb1 led open circuit but has paralleled zener upper otp not triggered and fb1 < 4v fb1 remains on and has highest vf, thus v out increases. fb2 through fb6 on, q2 through q6 burn power vf of fb1 6fb1 led open circuit but has paralleled zener upper otp triggered but fb1 < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will reduce iout further same as fb1 vf of fb1 7fb1 led open circuit but has paralleled zener upper otp not triggered but fbx > 4v fb1 remains on and has highest vf, thus v out increases. v out increases, then fb-x switches off after 6 pwm cycles. this is an unwanted shut off and can be prevented by setting ovp at an appropriate level. vf of fb1 8 channel-to-channel vf too high lower otp triggered but fbx < 4v any channel at below the targ et current will fault out after 6 pwm cycles. remaining channels driven with normal current. highest vf of fb1 through fb6 9 channel-to-channel vf too high upper otp triggered but fbx < 4v all channels go off until chip cooled and then comes back on with current reduced to 76%. subsequent otp triggers will redu ce iout further highest vf of fb1 through fb6 10 output led stack voltage too high v out > vovp any channel that is below the target current will time- out after 6 pwm cycles, and vout will return to the normal regualtion voltage re quired for ot her channels. highest vf of fb1 through fb6 11 v out /lx shorted to gnd at start-up or v out shorted in operation lx current and timing are monitored. ovp pins monitored for excursions below 20% of ovp threshold. the chip is permanentl y shutdown 31ms after powerup if vout/lx is shorted to gnd. table 3. protections table (continued) case failure mode detection mode failed channel action good channels action v out regulated by v l l i l t ? = (eq. 11) v ( i 0 ) l ? dt s v o v d v i ? ? () = l1 ( d ) t s ? ? ? (eq. 12) v o v i 11d ? () ? = ? (eq. 13) dv o ( v i ) v o ? ? = (eq. 14)
ISL97676 18 fn7600.0 march 12, 2010 input capacitor switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. this reduces interaction between the regulator and input supply, thereby improving system stability. the high switching fr equency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. a capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as x5r or x7r ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. in boost mode, input current flows continuously into the inductor; ac ripple component is only proportional to the rate of the inductor charging, thus, smaller value input capacitors may be used. it is recommended that an input capacitor of at least 10f be used. ensure the voltage rating of the input capacitor is suitable to handle the full supply range. inductor the selection of the inductor should be based on its maximum current (i sat ) characteristics, power dissipation (dcr), emi susceptibility (shielded vs unshielded), and size. inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. the inductor?s maximum current capability must be large enough to handle the peak current at the worst case condition. if an inductor co re is chosen with a lower current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and overheating in the core. the series resistance, dcr, within the inductor causes conduction loss and heat dissipation. a shielded inductor is usually more suitable for emi susceptible applications, such as led backlighting. the peak current can be derived from the voltage across the inductor during the off period, as expressed in equation 15: the choice of 85% is just an average term for the efficiency approximation. the first term is the average current, which is inversely proportional to the input voltage. the second term is the inductor current change, which is inversely proportional to l and f sw . as a result, for a given switching frequency, minimum input voltage must be used to caluclate the input/inductor current as shown in equation 15. fora given inductor size, the larger the inductance value, the higher the series resistance because of the extra number of turns required, thus, higher conductive losses. the ISL97676 current limit should be less than the inductor saturation current. output capacitors the output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. output ripple voltage consists of the discharge of the output capacitor during the fet ton period and the voltage drop due to load current flowing through the esr of the output capacitor. the ripple voltage is shown in equation 16: the above equation shows the importance of using a low esr output capacitor for minimizing output ripple. the choice of x7r over y5v ceramic capacitors is highly recommended because the former capacitor is less sensitive to capacitance change over voltage as shown in figure 27. y5v?s absolute capacitance can be reduced to 10%~20% of its rated capacitance at the maximum voltage. in any case, y5v type of ceramic capacitor should be avoided. here are some recommendations for various applications: for 20ma applications with v in > 7v, 1 x 4.7f (x7r type) is sufficient. for 20ma applications with v in < 7v, 2 x 4.7f (x7r type) is required in some configurations. channel capacitor it is recommended to use at least 1.5nf capacitors from ch pins to v out . larger capacitors will reduce led current ripple at boost frequency, but will degrade transient performance at high pwm frequencies. the best value is dependant on pcb layout. up to 4.7nf is sufficient for most configurations. output ripple v co , can be reduced by increasing co or f sw , or using small esr capacitors as shown in equation 16. in general, ceramic capacitors are the best choice for il peak v o ( i o ) 85% ( v i ) 12v i v o ( v i ) l ( v o f sw ) ? ? [] ? + ? = (eq. 15) v co i ( o c o df s ) i ( o esr () + ? ? = (eq. 16) figure 27. x7r and v5y types ceramic capacitors 0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 45 applied voltage (v) capacitance (f) poly. (ceramic y5v 2.2f 50v cap) poly. (ceramic x7r 2.2f 50v cap)
ISL97676 19 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7600.0 march 12, 2010 for additional products, see www.intersil.com/product_tree output capacitors in small to medium sized lcd backlight applications due to their cost, form factor, and low esr. a larger output capacitor will also ease the driver response during pwm dimming off period due to the longer sample and hold effect of the output drooping. the driver does not need to boost as much on the next on period which minimizes transient current. the output capacitor is also needed for compensation, and, in general one to two 4.7f/50v ceramic capacitors are needed for netbook or no tebook display backlight applications. schottky diode a high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. low forward voltage and reverse leakage current will minimize losses, making schottky diodes the preferred choice. although the schottky diode turns on only during the boost switch off period, it carries the same peak current as the inductor, therefore, a suitable current rated schottky diode must be used. applications high current applications each channel of the ISL97676 can support up to 30ma. for applications that need higher current, multiple channels can be grouped to achieve the desirable current. for example, the cathode of the last led can be connected to fb1 to fb3, this configuration can be treated as a single string with 90ma current driving capability. products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: ISL97676 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php figure 28. grouping multiple channels for high current applications fb1 fb2 fb3 v out revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/12/10 fn7600.0 initial release to web.
ISL97676 20 fn7600.0 march 12, 2010 package outline drawing l20.4x4c 20 lead quad flat no-lead plastic package rev 0, 11/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 4.00 a 4.00 b 6 pin 1 index area (4x) 0.15 4x 0.50 2.0 16x 20 16 15 11 pin #1 index area 6 2 .70 0 . 15 5 1 20x 0.25 +0.05 / -0.07 0.10 m ab c 20x 0.4 0.10 4 6 10 base plane seating plane 0.10 see detail "x" 0.08 c c c 0 . 90 0 . 1 0 . 2 ref c 0 . 05 max. 0 . 00 min. 5 ( 3. 8 typ ) ( 2. 70 ) ( 20x 0 . 6) ( 20x 0 . 5 ) ( 20x 0 . 25 )

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